/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
 * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
 * Author: Clément Le Goffic <clement.legoffic@foss.st.com> for STMicroelectronics.
 */

#ifndef _DT_BINDINGS_STM32MP13_HDP_H
#define _DT_BINDINGS_STM32MP13_HDP_H

/* define a macro for each function a HDP pin can transmit */
#define HDP0_PWR_PWRWAKE_SYS			 "0"
#define HDP0_PWR_STOP_FORBIDDEN			 "1"
#define HDP0_PWR_STDBY_WAKEUP			 "2"
#define HDP0_PWR_ENCOMP_VDDCORE			 "3"
#define HDP0_BSEC_OUT_SEC_NIDEN			 "4"
#define HDP0_AIEC_SYS_WAKEUP			 "5"
#define HDP0_DDRCTRL_LP_REQ			 "8"
#define HDP0_PWR_DDR_RET_ENABLE_N		 "9"
#define HDP0_DTS_CLK_PTAT			 "10"
#define HDP0_SRAM3CTRL_TAMP_ERASE_ACT		 "12"
#define HDP0_GPOVAL_0				 "15"

#define HDP1_PWR_SEL_VTH_VDDCPU			 "0"
#define HDP1_PWR_MPU_RAM_LOWSPEED		 "1"
#define HDP1_CA7_NAXIERRIRQ			 "2"
#define HDP1_PWR_OKIN_MR			 "3"
#define HDP1_BSEC_OUT_SEC_DBGEN			 "4"
#define HDP1_AIEC_C1_WAKEUP			 "5"
#define HDP1_RCC_PWRDS_MPU			 "6"
#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ		 "8"
#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR		 "9"
#define HDP1_SRAM3CTRL_HW_ERASE_ACT		 "12"
#define HDP1_NIC400_S0_BREADY			 "13"
#define HDP1_GPOVAL_1				 "15"

#define HDP2_PWR_PWRWAKE_MPU			 "0"
#define HDP2_PWR_MPU_CLOCK_DISABLE_ACK		 "1"
#define HDP2_CA7_NDBGRESET_I			 "2"
#define HDP2_BSEC_IN_RSTCORE_N			 "4"
#define HDP2_BSEC_OUT_SEC_BSC_DIS		 "5"
#define HDP2_DDRCTRL_DFI_INIT_COMPLETE		 "8"
#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH		 "9"
#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ		 "10"
#define HDP2_SRAM3CTRL_SW_ERASE_ACT		 "12"
#define HDP2_NIC400_S0_BVALID			 "13"
#define HDP2_GPOVAL_2				 "15"

#define HDP3_PWR_SEL_VTH_VDDCORE		 "0"
#define HDP3_PWR_MPU_CLOCK_DISABLE_REQ		 "1"
#define HDP3_CA7_NPMUIRQ0			 "2"
#define HDP3_CA7_NFIQOUT0			 "3"
#define HDP3_BSEC_OUT_SEC_DFTLOCK		 "4"
#define HDP3_BSEC_OUT_SEC_JTAG_DIS		 "5"
#define HDP3_RCC_PWRDS_SYS			 "6"
#define HDP3_SRAM3CTRL_TAMP_ERASE_REQ		 "7"
#define HDP3_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE0 "8"
#define HDP3_DTS_VALOBUS1_0			 "10"
#define HDP3_DTS_VALOBUS2_0			 "11"
#define HDP3_TAMP_POTENTIAL_TAMP_ERFCFG		 "12"
#define HDP3_NIC400_S0_WREADY			 "13"
#define HDP3_NIC400_S0_RREADY			 "14"
#define HDP3_GPOVAL_3				 "15"

#define HDP4_PWR_STOP2_ACTIVE			 "1"
#define HDP4_CA7_NL2RESET_I			 "2"
#define HDP4_CA7_NPORESET_VARM_I		 "3"
#define HDP4_BSEC_OUT_SEC_DFTEN			 "4"
#define HDP4_BSEC_OUT_SEC_DBGSWENABLE		 "5"
#define HDP4_ETH1_OUT_PMT_INTR_O		 "6"
#define HDP4_ETH2_OUT_PMT_INTR_O		 "7"
#define HDP4_DDRCTRL_STAT_DDRC_REG_SELFREF_TYPE1 "8"
#define HDP4_DDRCTRL_CACTIVE_0			 "9"
#define HDP4_DTS_VALOBUS1_1			 "10"
#define HDP4_DTS_VALOBUS2_1			 "11"
#define HDP4_TAMP_NRESET_SRAM_ERCFG		 "12"
#define HDP4_NIC400_S0_WLAST			 "13"
#define HDP4_NIC400_S0_RLAST			 "14"
#define HDP4_GPOVAL_4				 "15"

#define HDP5_CA7_STANDBYWFIL2			 "0"
#define HDP5_PWR_VTH_VDDCORE_ACK		 "1"
#define HDP5_CA7_NCORERESET_I			 "2"
#define HDP5_CA7_NIRQOUT0			 "3"
#define HDP5_BSEC_IN_PWROK			 "4"
#define HDP5_BSEC_OUT_SEC_DEVICEEN		 "5"
#define HDP5_ETH1_OUT_LPI_INTR_O		 "6"
#define HDP5_ETH2_OUT_LPI_INTR_O		 "7"
#define HDP5_DDRCTRL_CACTIVE_DDRC		 "8"
#define HDP5_DDRCTRL_WR_CREDIT_CNT		 "9"
#define HDP5_DTS_VALOBUS1_2			 "10"
#define HDP5_DTS_VALOBUS2_2			 "11"
#define HDP5_PKA_PKA_ITAMP_OUT			 "12"
#define HDP5_NIC400_S0_WVALID			 "13"
#define HDP5_NIC400_S0_RVALID			 "14"
#define HDP5_GPOVAL_5				 "15"

#define HDP6_CA7_STANDBYWFE0			 "0"
#define HDP6_PWR_VTH_VDDCPU_ACK			 "1"
#define HDP6_CA7_EVENTO				 "2"
#define HDP6_BSEC_IN_TAMPER_DET			 "4"
#define HDP6_BSEC_OUT_SEC_SPNIDEN		 "5"
#define HDP6_ETH1_OUT_MAC_SPEED_O1		 "6"
#define HDP6_ETH2_OUT_MAC_SPEED_O1		 "7"
#define HDP6_DDRCTRL_CSYSACK_DDRC		 "8"
#define HDP6_DDRCTRL_LPR_CREDIT_CNT		 "9"
#define HDP6_DTS_VALOBUS1_3			 "10"
#define HDP6_DTS_VALOBUS2_3			 "11"
#define HDP6_SAES_TAMPER_OUT			 "12"
#define HDP6_NIC400_S0_AWREADY			 "13"
#define HDP6_NIC400_S0_ARREADY			 "14"
#define HDP6_GPOVAL_6				 "15"

#define HDP7_CA7_STANDBYWFI0			 "0"
#define HDP7_PWR_RCC_VCPU_RDY			 "1"
#define HDP7_CA7_EVENTI				 "2"
#define HDP7_CA7_DBGACK0			 "3"
#define HDP7_BSEC_OUT_FUSE_OK			 "4"
#define HDP7_BSEC_OUT_SEC_SPIDEN		 "5"
#define HDP7_ETH1_OUT_MAC_SPEED_O0		 "6"
#define HDP7_ETH2_OUT_MAC_SPEED_O0		 "7"
#define HDP7_DDRCTRL_CSYSREQ_DDRC		 "8"
#define HDP7_DDRCTRL_HPR_CREDIT_CNT		 "9"
#define HDP7_DTS_VALOBUS1_4			 "10"
#define HDP7_DTS_VALOBUS2_4			 "11"
#define HDP7_RNG_TAMPER_OUT			 "12"
#define HDP7_NIC400_S0_AWAVALID			 "13"
#define HDP7_NIC400_S0_ARAVALID			 "14"
#define HDP7_GPOVAL_7				 "15"

#endif /* _DT_BINDINGS_STM32MP13_HDP_H */
